Tasks Completed

CPU design – Not completed yet

  • Full pipeline completed for standard MIPS instructions.
  • Interlocks and Bypass functions tested and confirmed working.
  • Up to 150mhz without TLB, FPU and Cache cores.
  • CP0 Core completed to send internal registers.
  • 64bit pipeline, but only 32 bit PC register (64 bit PC is not required for N64 games).
  • 64bit loads and stores fully working.
  • TLB Core started, but timing issues with it. Will need to redesign it.
  • FPU Core also started, but only for 32 bit ops. Working on increasing the pipeline to 64 for both ops to be done.
  • The FPU ALU  will be separate from the main ALU pipeline to simplify the FPGA logic and then able to do fault finding much easier.
  • Cache memory with duel clocks. This is so we can then start overclocking the CPU independent of the RCP core clock
  • Thanks To ElectronAsh we have the orginal CPU on a board that I can use to get the RCP , PIF and other external accesses done without needing to know if the CPU crashed due to my own bugs – Cannot wait for fixing this up. A big speed increase to the CPU will be done here

Bus Design – Done

  • 64 bit Ram access / DMA Channel
  • 32 bit address and register access to devices
  • 8 bit extended bit access for RDP/VI Z-buffer and Colour alpha extended bits

MI Interface – Done

  • Standard access to registers and local memories (IMEM/DMEM and Rom access)
  • Ram access is via the DMA Channel as this would be able to byte mask data
  • Interface for an original N64 CPU via the Nexys Video FMS Port
  • Confirmed all block and subblock access done (This is important for the cache memory access.

PIF/SI interface – Done – with bugs

  • BRAM Interface with DMA controller
  • An internal CPU that would make the PIF ram look like the CIC seed is correct
  • A new PIF controller using a 6502 core that dose access to the BRAM and external devices. 
  • DMA controller that both reads and writes 64bytes at a time (not 64bits) This would be an improvement
  • Custom BIOS for booting.

Rom Reader – Done

  • Do both 32 and 64 bit reads and writes via the Register bus and DMA controller.
  • Changeable timing for rom reads
  • We need to look at making this independent of the master clock (62.5mhz) so we can run higher speeds and keep the read latency time calculations.

Ram controller – Done

  • Full register setup – Both the ram regs and the ram module regs accessible
  • be able to read and write at the same time to the MIG7 ram controller
  • Full 1 gbit throughput (500mbyte read and 500mbyte write)
  • Multiple cores to read and write at the same time.
  • Jobs are queued up so the latency of the DDR3 ram can be mitigated. We have a high latency on DDR3, the final build will be DDR2 as this will be 9 clock cycles not 27 clocks.
  • With the RDP, masking on all bytes

RSP Core – divide unit to complete

  • Full DMA, Imem and Dmem are completed and working
  • We can get this core up to 90mhz – Overclocking I hear
  • SU core tested and working
  • Interlock working in the pipeline process. This includes the VU core as well
  • bypass also sorted for the EXE and WB stages in the main core
  • Main CPU core has been completely tested for ALU and load and stores
  • CP0 fully working – Even the DMA 😉
  • VU core has been built and some normal ALU ops are tested and confirmed, Just some special ops that need to be checked.
  • Just the divide core to complete.
  • Duel Opcodes are imperminted, with the exception of loads/Stores and MTC/MFC/CFC/CTC as we are not able to write to the reg file at the same time.

RDP Core – The last thing to do

  • The pipeline has been designed and tested. But does it work …. Will find out(UPDATE) we do have fill commands working, But there is an issue with masking.
  • Need to build the memory interface that can do both Z-buffer, Color image transfer and reads, Texture load and stores, Masked stores that are all byte aligned.
  • Copy and Fill needs to be done directly from the memory controller
  • Memory controller will be done after the SU and VU in the RSP are tested and done.
  • Some Fill commands have been tested and confirmed working

More to come -Working both a day job, losing weight and programming FPGA code at the same time is stressful enough.

But you are welcome to check out the videos of my progress on Youtube

https://www.youtube.com/user/mazamars312

The Worlds First FPGA N64